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Applied Formal Verification: for Digital Circuit Design
Douglas L. Perry
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Applied Formal Verification: for Digital Circuit Design
Douglas L. Perry
Formal verification is a digital design method. This tutorial shows designers how to apply Formal Verification, along with hardware description languages like Verilog and VHDL, to solve real-world design problems.
240 pages, 75 illustrations
Medie | Bøger Hardcover bog (Bog med hård ryg og stift omslag) |
Udgivet | 1. maj 2005 |
ISBN13 | 9780071443722 |
Forlag | McGraw-Hill Education - Europe |
Antal sider | 240 |
Mål | 154 × 231 × 23 mm · 512 g |
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